Formalizing Memory Accesses and Interrupts

Reto Achermann
(Systems Group, Department of Computer Science, ETH Zurich)
Lukas Humbel
(Systems Group, Department of Computer Science, ETH Zurich)
David Cock
(Systems Group, Department of Computer Science, ETH Zurich)
Timothy Roscoe
(Systems Group, Department of Computer Science, ETH Zurich)

The hardware/software boundary in modern heterogeneous multicore computers is increasingly complex, and diverse across different platforms. A single memory access by a core or DMA engine traverses multiple hardware translation and caching steps, and the destination memory cell or register often appears at different physical addresses for different cores. Interrupts pass through a complex topology of interrupt controllers and remappers before delivery to one or more cores, each with specific constraints on their configurations. System software must not only correctly understand the specific hardware at hand, but also configure it appropriately at runtime. We propose a formal model of address spaces and resources in a system that allows us to express and verify invariants of the system's runtime configuration, and illustrate (and motivate) it with several real platforms we have encountered in the process of OS implementation.

In Holger Hermanns and Peter Höfner: Proceedings 2nd Workshop on Models for Formal Analysis of Real Systems (MARS 2017), Uppsala, Sweden, 29th April 2017, Electronic Proceedings in Theoretical Computer Science 244, pp. 66–116.
Published: 15th March 2017.

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