Verifying Parallel Loops with Separation Logic

Stefan Blom
(University of Twente)
Saeed Darabi
(University of Twente)
Marieke Huisman
(University of Twente)

This paper proposes a technique to specify and verify whether a loop can be parallelised. Our approach can be used as an additional step in a parallelising compiler to verify user annotations about loop dependences. Essentially, our technique requires each loop iteration to be specified with the locations it will read and write. From the loop iteration specifications, the loop (in)dependences can be derived. Moreover, the loop iteration specifications also reveal where synchronisation is needed in the parallelised program. The loop iteration specifications can be verified using permission-based separation logic.

In Alastair F. Donaldson and Vasco T. Vasconcelos: Proceedings 7th Workshop on Programming Language Approaches to Concurrency and Communication-cEntric Software (PLACES 2014), Grenoble, France, 12 April 2014, Electronic Proceedings in Theoretical Computer Science 155, pp. 47–53.
Published: 12th June 2014.

ArXived at: http://dx.doi.org/10.4204/EPTCS.155.7 bibtex PDF
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