Formal and Informal Methods for Multi-Core Design Space Exploration

Jean-Francois Kempf
(VERIMAG)
Olivier Lebeltel
(VERIMAG)
Oded Maler
(VERIMAG)

We propose a tool-supported methodology for design-space exploration for embedded systems. It provides means to define high-level models of applications and multi-processor architectures and evaluate the performance of different deployment (mapping, scheduling) strategies while taking uncertainty into account. We argue that this extension of the scope of formal verification is important for the viability of the domain.

In Nathalie Bertrand and Luca Bortolussi: Proceedings Twelfth International Workshop on Quantitative Aspects of Programming Languages and Systems (QAPL 2014), Grenoble, France, 12-13 April 2014, Electronic Proceedings in Theoretical Computer Science 154, pp. 78–92.
Published: 6th June 2014.

ArXived at: https://dx.doi.org/10.4204/EPTCS.154.6 bibtex PDF
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