Andrew Bailey, George A. McCaskill & George J. Milne (1994):
An exercise in the automatic verification of asynchronous designs.
Formal Methods in System Design 4(3),
pp. 213–242,
doi:10.1007/BF01384047.
Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard & Marc Renaudin (2005):
An Asynchronous NoC Architecture Providing Low Latency Service and Its Multi-Level Design Framework.
In: Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems ASYNC'05 (New York, USA).
IEEE Computer Society Press,
pp. 54–63,
doi:10.1109/ASYNC.2005.10.
Damien Bergamini, Nicolas Descoubes, Christophe Joubert & Radu Mateescu (2005):
BISIMULATOR: A Modular Tool for On-the-Fly Equivalence Checking.
In: Nicolas Halbwachs & Lenore Zuck: Proceedings of the 11th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS'05), Edinburgh, Scotland, UK,
Lecture Notes in Computer Science 3440.
Springer Verlag,
pp. 581–585,
doi:10.1007/978-3-540-31980-1_42.
Kees van Berkel, Joep Kessels, Marly Roncken, Ronald Saeijs & Frits Schalij (1991):
The VLSI-Programming Language Tangram and its Translation into Handshake Circuits.
In: Proceedings of the Conference on European Design Automation (Amsterdam, The Netherlands).
IEEE Computer Society Press,
pp. 384–389,
doi:10.1109/EDAC.1991.206431.
Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu & Wendelin Serwe (2018):
Model-checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits.
In: Milos Krstic & Ian W. Jones: Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'18), Vienna, Austria.
IEEE,
pp. 34–42,
doi:10.1109/ASYNC.2018.00021.
Stephen D. Brookes, C. A. R. Hoare & A. W. Roscoe (1984):
A Theory of Communicating Sequential Processes.
Journal of the ACM 31(3),
pp. 560–599,
doi:10.1145/828.833.
David Champelovier, Xavier Clerc, Hubert Garavel, Yves Guerte, Christine McKinty, Vincent Powazny, Frédéric Lang, Wendelin Serwe & Gideon Smeding (2019):
Reference Manual of the LNT to LOTOS Translator (Version 6.8).
Available at http://cadp.inria.fr/publications/Champelovier-Clerc-Garavel-et-al-10.html.
INRIA, Grenoble, France.
Rance Cleaveland, Joachim Parrow & Bernhard Steffen (1989):
The Concurrency Workbench.
In: Joseph Sifakis: Proceedings of the 1st Workshop on Automatic Verification Methods for Finite State Systems, Grenoble, France,
Lecture Notes in Computer Science 407.
Springer Verlag,
pp. 24–37,
doi:10.1007/3-540-52148-8_3.
David L. Dill (1988):
Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits.
Acm distinguished dissertation.
Carnegie Mellon University, Pittsburgh, PA, USA.
Available at http://reports-archive.adm.cs.cmu.edu/anon/scan/CMU-CS-88-119.pdf.
Doug Edwards & Andrew Bardsley (2002):
Balsa: An Asynchronous Hardware Synthesis Language.
The Computer Journal 45(1),
pp. 12–18,
doi:10.1093/comjnl/45.1.12.
Hubert Garavel & Frédéric Lang (2001):
SVL: a Scripting Language for Compositional Verification.
In: Myungchul Kim, Byoungmoon Chin, Sungwon Kang & Danhyung Lee: Proceedings of the 21st IFIP WG 6.1 International Conference on Formal Techniques for Networked and Distributed Systems (FORTE'01), Cheju Island, Korea.
Kluwer Academic Publishers,
pp. 377–392.
Available at http://cadp.inria.fr/publications/Garavel-Lang-01.html.
Hubert Garavel, Frédéric Lang, Radu Mateescu & Wendelin Serwe (2013):
CADP 2011: A Toolbox for the Construction and Analysis of Distributed Processes.
Springer International Journal on Software Tools for Technology Transfer (STTT) 15(2),
pp. 89–107,
doi:10.1007/s10009-012-0244-z.
Hubert Garavel, Frédéric Lang & Wendelin Serwe (2017):
From LOTOS to LNT.
In: Joost-Pieter Katoen, Rom Langerak & Arend Rensink: ModelEd, TestEd, TrustEd – Essays Dedicated to Ed Brinksma on the Occasion of His 60th Birthday,
Lecture Notes in Computer Science 10500.
Springer Verlag,
pp. 3–26,
doi:10.1007/978-3-319-68270-9_1.
Hubert Garavel & Wendelin Serwe (2017):
The Unheralded Value of the Multiway Rendezvous: Illustration with the Production Cell Benchmark.
In: Holger Hermanns & Peter Höfner: Proceedings of the 2nd Workshop on Models for Formal Analysis of Real Systems (MARS'17), Uppsala, Sweden,
Electronic Proceedings in Computer Science 244,
pp. 230–270,
doi:10.4204/EPTCS.244.10.
Tingting Jia, Caihong Li & Anping He (2017):
Modeling and Verification of Circuit with Stable-Event.
In: Proceedings of the 2017 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC), Nanjing, China.
IEEE,
pp. 471–475,
doi:10.1109/CyberC.2017.73.
Mark B. Josephs (1992):
Receptive Process Theory.
Acta Informatica 29(1),
pp. 17–31,
doi:10.1007/BF01178564.
Mark B. Josephs (2007):
Gate-level Modelling and Verification of Asynchronous Circuits using CSPM and FDR.
In: Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), Berkeley, California, USA.
IEEE,
pp. 83–94,
doi:10.1109/ASYNC.2007.19.
Hemangee K. Kapoor & Mark B. Josephs (2004):
Modelling and Verification of Delay-Insensitive Circuits using CCS and the Concurrency Workbench.
Information Processing Letters 89(6),
pp. 293–296,
doi:10.1016/j.ipl.2003.12.007.
Frédéric Lang (2005):
EXP.OPEN 2.0: A Flexible Tool Integrating Partial Order, Compositional, and On-the-fly Verification Methods.
In: Judi Romijn, Graeme Smith & Jaco van de Pol: Proceedings of the 5th International Conference on Integrated Formal Methods (IFM'05), Eindhoven, The Netherlands,
Lecture Notes in Computer Science 3771.
Springer Verlag,
pp. 70–88,
doi:10.1007/11589976_6.
Alain J. Martin (1986):
Compiling Communicating Processes into Delay-Insensitive VLSI Circuits.
Distributed Computing 1(4),
pp. 226–234,
doi:10.1007/BF01660034.
Alain J. Martin (2014):
25 Years Ago: The First Asynchronous Microprocessor.
Computer Science Technical Reports 2014.001.
California Institute of Technology, Pasadena, California, USA.
Available at https://resolver.caltech.edu/CaltechAUTHORS:20140206-111915844.
David E. Muller (1955):
Theory of Asynchronous Circuits.
Research report 66.
University of Illinois at Urbana-Champaign, Department of Computer Science.
Available at https://archive.org/details/theoryofasynchro66mull.
Luis A. Plana, P. A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside & Z. C. Yu (2003):
SPA – a secure Amulet core for smartcard applications.
Microprocessors and Microsystems 27(9),
pp. 431–446,
doi:10.1016/S0141-9331(03)00093-0.
Marc Renaudin, Bertrand Folco & Boulahia Boubkar (2018):
Circuit intégré protégé.
Brevet d'invention 16 57129 3 054 344.
Institut National de la Propriété Industrielle.
Marc Renaudin, Bertrand Folco & Boulahia Boubkar (2019):
Circuit intégré protégé.
Fascicule de Brevet Europeen EP 3 276 656 B1.
European Patent Office.
Ken Stevens, John Aldwinckle, Graham Birtwistle & Ying Liu (1993):
Designing Parallel Specifications in CCS.
In: Proceedings of the Canadian Conference on Electrical and Computer Engineering,
pp. 983–986,
doi:10.1109/CCECE.1993.332460.
Tom Verhoeff (1998):
Analyzing Specifications for Delay-Insensitive Circuits.
In: Proceedings of the Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'98), San Diego, California, USA.
IEEE,
pp. 172–183,
doi:10.1109/ASYNC.1998.666503.
X. Wang, M. Kwiatkowska, G. Theodoropoulos & Q. Zhang (2006):
Opportunities and Challenges in Process-Algebraic Verification of Asynchronous Circuit Designs.
In: Proceedings of the Second Workshop on Globally Asynchronous Locally Synchronous Design (FMGALS'05),
Electronic Notes in Theoretical Computer Science 146,
pp. 189–206,
doi:10.1016/j.entcs.2005.05.042.
Xu Wang & Marta Z. Kwiatkowska (2007):
On Process-algebraic Verification of Asynchronous Circuits.
Fundamenta Informaticae 80(1–3),
pp. 283–310.
eptcs@eptcs.org